A CMOS solid state imaging device can be reduced more in size and power consumption than a CCD (Charge Transfer Device), and is therefore used as an imaging device in a digital still camera or a cellular phone.
In order to achieve a further reduction in size and power consumption in the CMOS solid state imaging device, it is necessary to reduce a power supply voltage by reducing an area per pixel according to the scaling law and reducing the dimensions of elements forming the pixel. A pixel region can be thus reduced and the sensitivity is reduced proportionally.
Incidentally, Japanese Patent No. 2618939 discloses a technique in the related art aimed at increasing the speeds and an image quality in a CCD. This technique can prevent mixing of signal charges (signal deterioration) among horizontal CCD registers when high-speed reading is performed using a CCD that has been reduced in size and increased in resolution.
The technique to prevent signal deterioration in the CCD has been disclosed; however, there is no satisfactory countermeasure against S/N deterioration when a quantity of charges that can be handled in the CMOS solid state imaging device is lessened. In other words, the CMOS solid state imaging device has an advantage that the pixel portion and peripheral circuits can be manufactured in the same process; however, when the pixel region is reduced according to the scaling law, a power supply voltage is reduced as well. This reduces a voltage applied to the transfer gate used when charges are read out from the pixel portion, which gives rise to S/N deterioration caused by a reduced quantity of saturation charges.